\doxysection{RNG\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_r_n_g___type_def}{}\label{struct_r_n_g___type_def}\index{RNG\_TypeDef@{RNG\_TypeDef}}


RNG.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_n_g___type_def_ab422a7aeea33d29d0f8b841bb461e3a8}{CR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_n_g___type_def_a4e4c38cd6a078fea5f9fa5e31bc0d326}{SR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_n_g___type_def_a89f3352fb11cca430aaecc0c9b49c6d3}{DR}}
\item 
\Hypertarget{struct_r_n_g___type_def_a8e3d9db3d6218f82a621fd454131123e}\label{struct_r_n_g___type_def_a8e3d9db3d6218f82a621fd454131123e} 
uint32\+\_\+t {\bfseries RESERVED}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_n_g___type_def_a9f1471aeaacfa0c1c19810c0ac080b25}{HTCR}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
RNG. 

\label{doc-variable-members}
\Hypertarget{struct_r_n_g___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_r_n_g___type_def_ab422a7aeea33d29d0f8b841bb461e3a8}\index{RNG\_TypeDef@{RNG\_TypeDef}!CR@{CR}}
\index{CR@{CR}!RNG\_TypeDef@{RNG\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR}{CR}}
{\footnotesize\ttfamily \label{struct_r_n_g___type_def_ab422a7aeea33d29d0f8b841bb461e3a8} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RNG\+\_\+\+Type\+Def\+::\+CR}

RNG control register, Address offset\+: 0x00 \Hypertarget{struct_r_n_g___type_def_a89f3352fb11cca430aaecc0c9b49c6d3}\index{RNG\_TypeDef@{RNG\_TypeDef}!DR@{DR}}
\index{DR@{DR}!RNG\_TypeDef@{RNG\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DR}{DR}}
{\footnotesize\ttfamily \label{struct_r_n_g___type_def_a89f3352fb11cca430aaecc0c9b49c6d3} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RNG\+\_\+\+Type\+Def\+::\+DR}

RNG data register, Address offset\+: 0x08 \Hypertarget{struct_r_n_g___type_def_a9f1471aeaacfa0c1c19810c0ac080b25}\index{RNG\_TypeDef@{RNG\_TypeDef}!HTCR@{HTCR}}
\index{HTCR@{HTCR}!RNG\_TypeDef@{RNG\_TypeDef}}
\doxysubsubsection{\texorpdfstring{HTCR}{HTCR}}
{\footnotesize\ttfamily \label{struct_r_n_g___type_def_a9f1471aeaacfa0c1c19810c0ac080b25} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RNG\+\_\+\+Type\+Def\+::\+HTCR}

RNG health test configuration register, Address offset\+: 0x10 \Hypertarget{struct_r_n_g___type_def_a4e4c38cd6a078fea5f9fa5e31bc0d326}\index{RNG\_TypeDef@{RNG\_TypeDef}!SR@{SR}}
\index{SR@{SR}!RNG\_TypeDef@{RNG\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SR}{SR}}
{\footnotesize\ttfamily \label{struct_r_n_g___type_def_a4e4c38cd6a078fea5f9fa5e31bc0d326} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RNG\+\_\+\+Type\+Def\+::\+SR}

RNG status register, Address offset\+: 0x04 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
